1. Field of the Invention
The present invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of forming polysilicon lines in which a thin oxide protection layer prevents damage to poly sidewalls and active area surfaces in the fabrication of integrated circuits.
2. Description of the Prior Art
In the fabrication of integrated circuits, photolithography and etching are used to form structures such as polysilicon gates, word lines, bit lines, local oxidation of silicon (LOCOS), shallow trench isolation (STI), and the like. A photoresist material is coated over the layer or layers to be etched. The photoresist material is exposed to actinic light through a mask, then developed to form the photoresist mask for etching the underlying layer or layers. An anti-reflective coating (ARC) layer, typically silicon oxynitride (SiON) is used under the photoresist layer to improve the photolithography process window for the polysilicon layer. However, removal of the SiON after etching, usually using hot H.sub.3 PO.sub.4 wet etching, induces sidewall damage to the polysilicon lines and top roughness of the active area.
U.S. Pat. No. 5,767,018 to Bell discusses a pitting of the active area surface that is believed to result from the interaction of the main polysilicon etch with the SiON ARC layer. Their solution is to use an etching recipe in which a polymer is formed on the sidewalls of the polysilicon lines during etching to prevent the pitting. U.S. Pat. No. 5,605,601 to Kawasaki discloses a method of etching multi-layered polysilicon gates. U.S. Pat. Nos. 5,437,765 and 5,741,396 to Loewenstein teach a method in which a SiON top layer is etched selectively with respect to silicon oxide and polysilicon.